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FUJITSU SEMICONDUCTOR DATA SHEET
Revision 3.0
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89980 Series
MB89983/P985/PV980
s DESCRIPTION
The MB89980 series is a line of the general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as an LCD controller/driver, an A/D converter, timers, remote control transmission output, buzzer output, PWM timers, and external interrupts.
s FEATURES
* * * * * * * * * * * * * * * * * * F2MC-8L family CPU core Dual-clock control system Maximum memory size: 8-Kbyte ROM, 256-byte RAM (max.) Minimum execution time: 0.95 s/4.2 MHz I/O ports: max. 47 channels (max. 13 high-current type) 21-bit time-base counter 8/16-bit timer/counter: 8bit x 2 channels or 16-bit x 1 channels External interrupts (wake-up function): Four channels with edge selection plus eight level-interrupt channels 8-bit A/D converter: 4 channels 8-bit PWM timers: 2 channels Watch prescaler (15 bits) LCD controller/driver: 14 segments x 4 commons (max. 56 pixels) LCD driving reference voltage generator Remote control transmission output Buzzer output Power-on reset function (option) Low-power consumption modes (stop, sleep, and watch mode) CMOS technology
s PACKAGE
64-pin Ceramic MQFP 64-pin Plastic LQFP 64-pin Plastic QFP
(MQP-64C-P01)
(MQP-64C-P01)
(FPT-64P-M03)
(FPT-64P-M03)
(FPT-64P-M09) (FPT-64P-M09)
MB89980 Series
s PRODUCT LINEUP
Part number Parameter Classification ROM size RAM size CPU functions MB89983 Mass production products (mask ROM products) 8 K x 8 bits (internal mask ROM) 256 x 8 bits Number of instructions: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Interrupt processing time: MB89P985 One-time PROM product (OTP) 16K x 8 bits (Internal PROM) 512 x 8 bits 136 8 bits 1 to 3 bytes 1, 8,16 bits 0.95 s/4.2 MHz 9 s/4.2 MHz MB89PV980 Piggyback/evaluation product (for development) 32K x 8 bits (External ROM)
Ports
General-purpose I/O ports (N-ch open-drain): 8 (4 ports also serve as peripherals, 3 ports are heavy-current drive type.) Output-only ports (N-ch open-drain): 20 (4 ports also serve as A/D, 14 ports serve as segment pins and 2 ports serve as common pins, 10 ports are heavycurrent drive type .) General-purpose I/O ports (CMOS): 16 (12 ports also serve as an external interrupt, ) Input-only ports (CMOS) 2 (serve with sub-clock pins) Output-only ports (CMOS) 1 (serves as peripherials Total: 47 (max.) 8-bit timer operation (toggled output capable, operating clock cycle 1.9 s to 486 s) 16-bit timer operation (toggled output capable, operating clock cycle 1.9 s to 486 s) Common output: Segment output: Bias power supply pins: LCD display RAM size: Dividing resistor for LCD driving: 4 (max.) 14 (max.) *2 4 14 x 4 bits Built-in (an external resistor selectability)
Timer/counter LCD controller/driver
A/D converter
8-bit resolution x 4 channels A/D conversion mode (conversion time 43 s/4.2 MHz (44 instruction cycles)) Sense mode (conversion time 11.9 s/4.2 MHz) Continuous activation by an internal timer capable Reference voltage input 8 bits x 2 channels 8-bit reload timer operation (toggled output capable, operating clock cycle: 0.95 s to 124 ms) 8-bit resolution PWM operation (conversion cycle: 243 s to 32 s)
PWM timer 1, PWM timer 2
(Continued)
2
MB89980 Series
(Continued)
Part number Parameter External interrupt 1 (wake-up function) MB89983 MB89P985 MB89PV980
4 independent channels (edge selectability) Rising edge/falling edge selectability Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.) "L" level interrupts x 8 channels 1 (7 frequencies are selectable by the software.) 1 (Pulse width and cycle are software selectable.) Subclock mode, sleep mode, stop mode, and watch mode CMOS
External interrupt 2 Buzzer output Remote control transmission output Standby modes Process Operating voltage
*1
2.2 V to 6.0 V
2.7 V to 6.0 V
*1: Varies with conditions such as the operating frequency. (The operating voltage of the A/D converter is assured separately. See section "s Electrical Characteristics.") *2: See section "s Mask Options."
s PACKAGE AND CORRESPONDING PRODUCTS
Package FPT-64P-M09 FPT-64P-M03 MQP-64C-P01 : Available x : Not available x x MB89983 MB89P985 MB89PV980 x x
Note: For more information about each package, see section "s Package Dimensions."
3
MB89980 Series
s DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, verify its differences from the product that will actually be used. Take particular care on the following points: * The stack area, etc., is set at the upper limit of the RAM.
2. Current Consumption
* In the case of the MB89PV980, add the current consumed by the EPROM which is connected to the top socket. * When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume more current than the product with a mask ROM. However, the current consumption in the sleep/stop modes is the same. (For more information, see section "s Electrical Characteristics.")
3. Mask Options
Functions that can be selected as options and how to designate these options vary by the product. Before using options check section "s Mask Options." Take particular care on the following points: * A pull-up resistor is not selectable for P40 to P47 and P60 to P65 if they are used as LCD pins. * A pull-up resistor is not selectable for P50 to P53 if they are used as analog input.
4. Pull-up resistor
Pull-up resisitors of MB89P985 and MB89PV980 are selected by pull-up control registor (Port 0, 1, 5), but there are no pull-up resistor for Port 2, 4 and 6 in MB89P985 and MB89PV980. ALL pull-up resistor of MB89983 are selected by mask option (Port 0, 1, 2, 4, 5, 6)
5. Segment/Common port
The Segment/Port , Common/Port output in MB89P985 and MB89PV980 are selected by control register, LCR2. The Segment/Port , Common/Port output in MB89983 are selected by mask option.
4
MB89980 Series
s PIN ASSIGNMENT
*1: Heavy-current drive type *2: When the dual clock system is selected *3, *4, *5, *6: Selected using mask option in MB89983, but selected by software in MB89P985 and MB89PV980.
P31/X0A*2 P32/X1A*2 RST MOD0 MOD1 X0 X1 Vss P02/INT22 P03/INT23 P04/INT24 P05/INT25 P06/INT26 P07/INT27 P10/INT10 P11/INT11
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P60/SEG8*1 *3 P61/SEG9*1 *3 P62/SEG10*6 P63/SEG11*6 P64/SEG12*6 P65/SEG13*6 P50/AN0 P51/AN1 P52/AN2 P53/AN3 AVcc AVR AVss P00/INT20 P01/INT21 P30/PWM1/BZ
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P47/SEG7*1 *4 P46/SEG6*1 *4 P45/SEG5*1 *4 P44/SEG4*1 *4 P43/SEG3*1 *5 P42/SEG2*1 *5 P41/SEG1*1 *5 P40/SEG0*1 *5 Vcc P71/COM3*3 P70/COM2*3 COM1 COM0 V3 V2 Vss
TOP VIEW QFP-64
(FPT-64P-M09) (FPT-64P-M03)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
V1 V0 P27/PWM2*1 P26*1 P25 P24/RCO P23 P22/TO P21*1 P20/EC P17 P16 P15 P14 P13/INT13 P12/INT12
5
MB89980 Series
(Top view)
P46/SEG6*1*4 P45/SEG5*1*4 P44/SEG4*1*4 P43/SEG3*1*5 P42/SEG2*1*5 P41/SEG1*1*5 P40/SEG0*1*5 VCC P71/COM3*3 P70/COM2*3 COM1 COM0 V3 P47/SEG7*1*4 P60/SEG8*1*3 P61/SEG9*1*3 P62/SEG10*6 P63/SEG11*6 P64/SEG12*6 P65/SEG13*6 P50/AN0 P51/AN1 P52/AN2 P53/AN3 AVCC AVR AVSS P00/INT20 P01/INT21 P30/PWM1/BZ P31/X0A*2 P32/X1A*2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
85 86 87 88 89 90 91 92 93
77 76 75 74 73 72 71 70 69
V2 VSS V1 V0 P27/PWM2*1 P26*1 P25 P24/RCO P23 P22/TO P21*1 P20/EC P17 P16 P15 P14 P13/INT13 P12/INT12 P11/INT11
*1: Heavy-current drive type *2: When the dual clock system is selected *3, *4,*5, *6: Selected using mask option in MB89983, but selected by software in MB89P985 and MB89PV980.
*
Pin assignment on package top (MB89PV980 only)
Pin no. 65 66 67 68 69 70 71 72 Pin name N.C. VPP A12 A7 A6 A5 A4 A3 Pin no. 73 74 75 76 77 78 79 80 Pin name A2 A1 A0 N.C. O1 O2 O3 VSS Pin no. 81 82 83 84 85 86 87 88 Pin name N.C. O4 O5 O6 O7 O8 CE A10 Pin no. 89 90 91 92 93 94 95 96 Pin name OE N.C. A11 A9 A8 A13 A14 VCC
N.C.: Internally connected. Do not use.
6
RST MOD0 MOD1 X0 X1 VSS P02/INT22 P03/INT23 P04/INT24 P05/INT25 P06/INT26 P07/INT27 P10/INT10
20 21 22 23 24 25 26 27 28 29 30 31 32
(MQP-64C-P01)
94 95 96 65 66 67 68
84 83 82 81 80 79 78
MB89980 Series
s PIN DESCRIPTION
Pin no. LQFP*1 MQFP*3 QFP*2 22 23 Pin name MB89983 I/O circuit type MB89P985 MB89PV980 Function
X0 A
23 20 21
24 21 22
X1 MOD0 C MOD1
Crystal or other resonator connector pins for the main clock The external clock can be connected to X0. When this is done, be sure to leave X1 open. CR oscillation selectability in model with a mask ROM only. A hysteresis input type Memory access mode setting pins Connect directly to VSS. Reset I/O pin This pin is an N-ch open-drain output type with a pullup resistor, and a hysteresis input type. "L" is output from this pin by an internal reset request (optional). The internal circuit is initialized by the input of "L". F General-purpose I/O ports Also serve as an external interrupt 2 input (wake-up function). External interrupt 2 input is hysteresis input. General-purpose I/O ports Also serve as an external interrupt 2 input (wake-up function). External interrupt 2 input is hysteresis input. General-purpose I/O ports Also serve as input for external interrupt 1 input (wake-up function). External interrupt 1 input is hysteresis input. General-purpose I/O ports N-ch open-drain general-purpose I/O port Also serve as the external clock input for the 8/16-bit timer/counter. The peripheral is a hysteresis input. N-ch open-drain general-purpose I/O port N-ch open-drain general-purpose I/O port Also serves as an 8/16-bit timer/counter output. N-ch open-drain general-purpose I/O port N-ch open-drain general-purpose I/O port Also serves as Remote control output. N-ch open-drain general-purpose I/O port N-ch open-drain general-purpose I/O port Also serves as the square wave or PWM wave output for the 8-bit PWM timer 2.
19
20
RST
D
14 to 15 15 to 16
P00/INT20 to P01/INT21 P02/INT22 to P07/INT27
E
25 to 30 26 to 31
E
F
31 to 34 32 to 35
P10/INT10 to P13/INT13 P14 to P17
E
F
35 to 38 36 to 39
G
H
39
40
P20/EC
J
K
40 41 42 43
41 42 43 44
P21 P22/TO P23 P24/RCO P25 to P26 P27/PWM2
L L L L L L
M M M M M M
44 to 45 45 to 46 46 47
(Continued)
*1: FPT-64P-M03 *2: FPT-64P-M09 *3: MQP-64C-P01
7
MB89980 Series
(Continued)
Pin no. LQFP* QFP*2 16
1
I/O circuit type Pin name MB89983 MB89P985 MB89PV980 I Function General-purpose CMOS Output port Also serves as the square wave or PWM wave output for the 8-bit PWM timer 1, or buzzer output.. General-purpose CMOS Input port (Hysteresis input type) Crystal or other resonator connector pins for the subclock (Subclock: 32.768 kHz) The external clock can be connected to X0A. When this is done, Be sure to leave X1A open. General-purpose CMOS Input port (Hysteresis input type) Crystal or other resonator connector pins for the subclock (Subclock: 32.768 kHz) The external clock can be connected to X0A. When this is done, Be sure to leave X1A open. N-ch open-drain general-purpose output ports Also serve as the analog input for the A/D converter. N-ch open-drain general-purpose output ports (High current type) Also serve as an LCD controller/driver segment output. N-ch open-drain general-purpose output ports (High-current type) Also serve as an LCD controller/driver segment output. N-ch open-drain general-purpose output ports Also serve as an LCD controller/driver segment output. N-ch open-drain general-purpose output ports Also serve as an LCD controller/driver common output. LCD controller/driver common output
MQFP*3 17
P30/PWM1/ BZ
P31 17 18 X0A
S
B
P32 18 19 X1A
S
B
7 to 10
8 to 11
P50/AN0 to P53/AN3 P40/SEG0 to P47/SEG7 P60/SEG8 to P61/SEG9 P62/SEG10 to P65/SEG13 P70/COM2, P71/COM3 COM0, COM1
P
Q
57 to 64
58 to 64 and 1
N/O
T/O
1 to 2
2 to 3
N/O
T/O
3 to 6
4 to 7
N/O
T/O
54, 55 52, 53
55, 56 53, 54
N/O O
T/O
(Continued)
*1: FPT-64P-M03 *2: FPT-64P-M09 *3: MQP-64C-P01
8
MB89980 Series
(Continued)
Pin no. LQFP*1 QFP2*2 47, 48, 50, 51 56 MQFP*3 48, 49 51, 52 57 Pin name I/O circuit type MB89983 MB89P985 MB89PV980 Function
V0 to V3
--
--
LCD driving power supply pins.
Vcc
--
--
Power supply pin
24, 49
25, 50
Vss
--
--
Power supply (GND) pin
11
12
AVcc
--
--
A/D converter power supply pin
12 13
13 14
AVR AVss
-- --
-- --
A/D converter reference voltage input pin A/D converter power supply pin Use this pin at the same voltage as VSS.
*1: FPT-64P-M03 *2: FPT-64P-M09 *3: MQP-64C-P01
9
MB89980 Series
s I/O CIRCUIT TYPE
Type
X1 N-ch P-ch
Circuit
Remarks Main clock (main clock crystal oscillator) * At an oscillation feedback resistor of approximately 1 M/5.0 V * CR oscillation is selectable for MB89983 only Subclock (subclock crystal oscillator) * At an oscillation feedback resistor of approximately 4.5 M/5.0 V
A
X0
P-ch N-ch
X1A N-ch P-ch
B
X0A
P-ch N-ch N-ch
C
* Hysteresis input * At a pull-down resistor (P-ch) of approximately 50 k/5.0 V
R P-ch
D
N-ch
* At an output pull-up resistor (P-ch) of approximately 50 k/5.0 V * Hysteresis input
R
P-ch P-ch
E
N-ch Port Peripheral R
* CMOS output * CMOS input * The peripheral is a hysteresis input type. * Pull-up resistor is approximately 50 k/5.0 V * Pull-up resistor is selected by mask option.
P-ch
Pull-up control register P-ch
F
N-ch Port Peripheral
* CMOS output * CMOS input * The peripheral is a hysteresis input type. * Pull-up resistor is approximately 50 k/5.0 V * Pull-up resisitor is selected by pull-up control register
(Continued)
10
MB89980 Series
(Continued)
Type
R P-ch P-ch
Circuit
Remarks
G
N-ch Port R
* CMOS output * CMOS input * Pull-up resistor is approximately 50 k/5.0 V * Pull-up resistor is selected by mask option.
P-ch
Pull-up control register P-ch
H
N-ch Port P-ch
* CMOS output * CMOS input * Pull-up resistor is approximately 50 k/5.0 V * Pull-up resisitor is selected by pull-up control register
I
N-ch
* CMOS output
R
P-ch
J
N-ch Port Peripheral
* N-ch open-drain output * CMOS input * The peripheral is a hysteresis input type. * Pull-up resistor is approximately 50 k/5.0 V * Pull-up resistor is selected by mask option.
K
N-ch Port Peripheral
* N-ch open-drain output * CMOS input * The peripheral is a hysteresis input type. * N-ch open-drain output * CMOS input * P21, P26, and P27 are a heavy-current drive type. * Pull-up resistor is approximately 50 k/5.0 V * Pull-up resistor is selected by mask option.
R
P-ch
L
N-ch Port
(Continued)
11
MB89980 Series
(Continued)
Type Circuit Remarks
M
N-ch Port
* N-ch open-drain output * CMOS input * P21, P26, and P27 are a heavy-current drive type.
R
P-ch
N
N-ch
* N-ch open-drain output * Pull-up resistor is approximately 50 k/5.0 V * Pull-up resistor is selected by mask option.
P-ch N-ch
O
P-ch N-ch
* LCD controller/driver common/segment output
R
P-ch
P
P-ch N-ch Analog input
* N-ch open-drain output * Analog input (A/D converter) * Pull-up resistor is approximately 50 k/5.0 V * Pull-up resistor is selected by mask option.
R
P-ch
Pull-up control register
Q
P-ch N-ch Analog input
* N-ch open-drain output * Analog input (A/D converter) * Pull-up resistor is approximately 50 k/5.0 V * Pull-up resisitor is selected by pull-up control register
S
* Hysteresis input
T
N-ch
* N-ch open-drain output
12
MB89980 Series
s HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on " 1. Absolute Maximum Ratings" in section "s Electrical Characteristics" is applied between VCC to VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D Converters
Connect to be AVCC = VCC and AVSS = AVR = VSS even if the A/D converters are not in use.
4. Treatment of N.C. Pin
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
6. Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and wake-up from stop mode.
7. Treatment of two Vss pins
Two Vss pins should be connected together externally.
8. Treatment of input port pins in standby mode
To avoid current leakage, it is recommended to remain a known logic level of input port pins during the standby mode.
13
MB89980 Series
s PROGRAMMING TO THE EPROM ON THE MB89P985
The MB89P985 is an OTPROM version of the MB89980 series.
1. Features
* 16-Kbyte PROM on chip * Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in EPROM mode is diagrammed below.
Address in normal mode 0000H I/O 0080H RAM 0100H
Generalpurpose
0200H registers 0280H EPROM mode (Corresponding addresses on the EPROM programmer) 8000H 0000H
Prohibited
Vacant area read FFH 4000H
C000H
ROM
FFFFH
7FFFH
Prog. area (PROM)
3. Programming to the EPROM
In EPROM mode, the MB89P985 functions equivalent to the MBM27C256A. This allows the PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. * Programming procedure (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 4000H to 7FFFH (note that addresses C000H to FFFFH while operating as a single chip assign to 4000H to 7FFFH in EPROM mode). (3) Program with the EPROM programmer.
14
MB89980 Series
s HANDLING THE MB89P985
1. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure.
Program, verify
Aging +150C, 48 Hrs.
Data verification
Assembly
2. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times.
3. EPROM Programmer Socket Adapter
Package FPT-64P-M03 FPT-64P-M09 Compatible socket adapter TBD TBD
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
15
MB89980 Series
s PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C256A-20TV
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato Co., Ltd.) listed below. Package LCC-32 (Rectangle) Adapter socket part number ROM-32LC-28DP-YG
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
3. Memory Space
Memory space in each mode, such as 32-Kbyte PROM, option area is diagrammed below.
Address 0000H
Single chip
Corresponding addresses on the EPROM programmer
I/O 0080H RAM 0280H Not available 8000H 0000H
PROM 32 KB
EPROM 32 KB
FFFFH
7FFFH
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 0000H to 7FFFH. (3) Program to 0000H to 7FFFH with the EPROM programmer.
16
MB89980 Series
s BLOCK DIAGRAM
Main clock
X0 X1
Oscillator (max. 4.2 MHz) Clock controller
21-bit timebase timer N-ch open-drain I/O port
P31/X0A*2 P32/X1A*2
Sub-clock Oscillator Watch Prescaler timer Port 3 8-bit PWM timer 1 Buzzer output Internal data bus
CMOS Input port (P30 is CMOS output port)
8-bit PWM timer 2 Port 2 Remote control output (Timer 2) timer/counter 2 8-bit (Timer 1) timer/counter 1 8-bit
4
P27/PWM2*1 P26*1 P24/RCO P25 P23 P21*1
P30/PWM1/BZ
P20/EC P22/TO
V0 to V3 COM0 to COM1 P40/SEG0 to P43/SEG3*1 *4 P44/SEG4 to P47/SEG7*1 *5 P60/SEG8 to P61/SEG9*1 *3 P62/SEG10 to P63/SEG11*6 P64/SEG12 to P65/SEG13*6 P70/COM2 to P71/COM3*3
RST
Reset circuit (Watchdog timer) Port 0
8 8
LCD controller/driver
2 4 4 2 2 2 2
Port 4
P00/INT20 to P07/INT27
External interrupt 2 (wake-up function) CMOS I/O port
8
6 2
Port 6, 7
Port 1
P10/INT10 to P13/INT13
4
4
External interrupt 1 (wake-up function) CMOS I/O port
14 x 4-bit display RAM (7 bytes)
4
P14 to P17
N-ch open-drain output ports RAM N-ch open-drain output port Port 5
4
F2MC-8L CPU
4
8-bit A/D converter
P50/AN0 to P53/AN3 AVCC
ROM Other pins MOD0, MOD1, VCC, VSS x 2
AVR AVSS
*1: Heavy-current drive type *2: When the dual clock system is selected *3, *4, *5, *6: Selected using mask option in MB89983, but selected by software in MB89P985 and MB89PV980.
17
MB89980 Series
s CPU CORE
1. Memory Space
The microcontrollers of the MB89980 series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89980 series is structured as illustrated below.
MB89983 0000H I/O 0080H RAM
Registers
MB89P985 0000H I/O 0080H RAM 0100H
Registers
MB89PV980 0000H I/O 0080H RAM
Registers
0100H 0180H
0100H 0200H 0280H
0200H 0280H
Access prohibited Access prohibited
Access prohibited
8000H C000H
E000H ROM FFC0H FFFFH FFC0H FFFFH ROM FFC0H FFFFH ROM
Vector table (reset, interrupt, vector call instruction)
18
MB89980 Series
2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided: Program counter (PC): Accumulator (A): A 16-bit register for indicating instruction storage positions A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 18-bit data processing instruction, the lower byte is used. Index register (IX): Extra pointer (EP): Stack pointer (SP): Program status (PS): A 16-bit register for index modification A 16-bit pointer for indicating a memory address A 16-bit register for indicating a stack area A 16-bit register for storing a register pointer, a condition code
16 bits PC A T IX EP SP PS : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status
Initial value FFFDH Undefined Undefined Undefined Undefined Undefined I-flag = 0, IL1, 0 = 11 Other bits are undefined.
The PS can further be divide into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.)
Structure of the Program Status Register
15 PS
14
13 RP
12
11
10
9
8
7 H
6 I
5
4
3 N
2 Z
1 V
0 C
Vacancy Vacancy Vacancy
IL1, 0
RP
CCR
19
MB89980 Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below.
Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP Lower OP codes b1 b0
"0" "0" "0" "0" "0" "0" "0" "1" R4 R3 R2 R1 R0 b2
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared otherwise. This flag is for decimal adjustment instructions. I-flag: IL1, 0: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0 when reset. Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit.
IL1 0 0 1 1
IL0 0 1 0 1
Interrupt level 1 2 3
High-low High
Low = no interrupt
N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0. Z-flag: V-flag: Set when an arithmetic operation results in 0. Cleared otherwise. Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does not occur.
C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise. Set the shift-out value in the case of a shift instruction.
20
MB89980 Series
The following general-purpose registers are provided: General-purpose registers: An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers. Up to a total of 16 banks can be used on the MB89983 (RAM 256 x 8 bits). Up to a total of 32 banks can be used on the MB89P985 and MB89PV980 (RAM 512 x 8 bits). The bank currently in use is indicated by the register bank pointer (RP). Note: The number of register banks that can be used varies with the RAM size.
Register Bank Configuraiton
This address = 0100H + 8 x (RP) R0 R1 R2 R3 R4 R5 R6 R7
16 banks (MB89983) 16 banks (MB89163) 32 banks (MB89P985 32 banks (MB89165) and MB89PV980)
Memory area
21
MB89980 Series
s I/O MAP
Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H to 17H 18H 19H 1AH 1BH 1CH - 1DH 1EH 1FH 20H 21H 22H to 2CH 2DH 2EH 2FH 30H 31H R/W R/W R/W R/W R/W R/W W R/W W CNTR1 COMR1 CNTR2 COMR2 (Vacancy) ADC1 ADC2 ADCD EIE1 EIF1 A/D control register 1 A/D control register 2 A/D data register External interrupt 1 control register External interrupt 1 flag register R/W R/W R/W R/W T2CR T1CR T2DR T1DR R/W R/W R/W R/W PDR6 PDR7 RCR1 RCR2 R/W R/W R/W PDR4 PDR5 BZCR R/W R/W R/W R/W R/W R/W SYCC STBC WDTC TBTC WPCR PDR3 Read/write R/W W R/W W R/W W Register name PDR0 DDR0 PDR1 DDR1 PDR2 DDR2 Register description Port 0 data register Port 0 data direction register Port 1 data register Port 1 data direction register Port 2 data register Port 2 data direction register (Vacancy) System clock control register Standby control register Watchdog timer control register Timebase timer control register Watch prescaler control register Port 3 data register (Vacancy) Port 4 data register Port 5 data register Buzzer register (Vacancy) Port 6 data register Port 7 data register Remote control transmission register 1 Remote control transmission register 2 (Vacancy) Timer 2 control register Timer 1 control register Timer 2 data register Timer 1 data register (Vacancy) PWM 1 control register PWM 1 compare register PWM 2 control register PWM 2 compare register
(Continued)
22
MB89980 Series
(Continued)
Address 32H 33H 34H to 3FH 40H 41H 42H 43H to 5FH 60H to 66H 67H to 71H 72H 73H 74H to 7BH 7CH 7DH 7EH 7FH W W W Access prohibited ILR1 ILR2 ILR3 ITR R/W R/W LCR1 LCR2 R/W VRAM R/W R/W R/W PURR0 PURR1 PURR5 Read/write R/W R/W Register name EIE2 EIF2 Register description External interrupt 2 control register External interrupt 2 flag register (Vacancy) Pull-up control register 0 (For MB89P985/PV980 only) Pull-up control register 1 (For MB89P985/PV980 only) Pull-up control register 5 (For MB89P985/PV980 only) (Vacancy) Display RAM (Vacancy) LCD control register 1 LCD control register 2 (For MB89P985/PV980 only) (Vacancy) Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Interrupt test register
Notes: Do not use vacancies. Notes: Read/write access symbols : R/W : Readable and writable R : Read-only W : Write-only
23
MB89980 Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V) Parameter Symbol VCC Power supply voltage LCD power supply voltage AVCC AVR V0 to V3 VI1 Input voltage VI2 VSS - 0.3 VSS + 7.0 V Value Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 Max. VSS + 7.0 VSS + 7.0 VSS + 7.0 VSS + 7.0 VCC + 0.3 Unit V V V V V AVCC must not exceed VCC + 0.3 V. AVR must not exceed AVCC + 0.3 V. V0 to V3 must not exceed VCC. VI1 must not exceed VSS + 7.0 V. All pins except P20 to P27 without a pull-up resistor P20 to P27 without a pull-up resistor VO1 must not exceed VSS + 7.0 V. All pins except P20 to P27, P40 to P47, P60 to P65, P70 and P71 without a pull-up resistor P20 to P27, P40 to P47, P60 to P65, P70 and P71 without a pull-up resistor All pins except P21, P26, P27, P40 to P47, P60 and P61 P21, P26, P27, P40 to P47, P60 and P61 All pins except P21, P26, P27, P40 to P47, P60, P61 and power supply pins Average value (operating current x operating rate) P21, P26, P27, P40 to P47, P60 and P61 Average value (operating current x operating rate) Peak value Average value (operating current x operating rate) All pins except P30 and power supply pins P30 Remarks
VO1 Output voltage VO2 IOL1 "L" level maximum output current IOL2
VSS - 0.3
VCC + 0.3
V
VSS - 0.3
VSS + 7.0 10 20
V mA mA
IOLAV1 "L" level average output current IOLAV2 "L" level total maximum output current "L" level total average output current IOL IOLAV IOH1 IOH2
4
mA

8 100 40 -5 -10
mA mA mA mA mA
"H" level maximum output current
(Continued)
24
MB89980 Series
(Continued)
(AVSS = VSS = 0.0 V) Parameter Symbol Value Min. -- Max. -2 Unit Remarks All pins except P30 and power supply pins Average value (operating current x operating rate) P30 Average value (operating current x operating rate) Peak value Average value (operating current x operating rate)
IOHAV1 "H" level average output current IOHAV2 "H" level total maximum output current "H" level total average output current Power consumption Operating temperature Storage temperature IOH IOHAV PD TA Tstg
mA
-- -- -- -- -40 -55
-4 -50 -10 300 +85 +150
mA mA mA mW C C
Precautions: Parmanent device damage may occur if the above "Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V) Parameter Symbol Value Min. 2.2*1 Power supply voltage VCC AVCC AVR LCD power supply voltage Operating temperature V0 to V3 TA 2.2*1 1.5 2.0 VSS -40 Max. 6.0*1 4.0 6.0 AVCC VCC +85 Unit V V V V V C Remarks Normal operation assurance range*1 Dual-clock mask ROM products Retains the RAM state in stop mode Normal operation assurance range V0 to V3 pins LCD power supply range (The optimum value dependent on the LCD element in use.)
*1: The minimum operating power supply voltage varies with the execution time (instruction cycle time) setting for the operating frequency. A/D converter assurance accuracy varies with the operating power supply voltage.
25
MB89980 Series
6 Analog accurancy assured in the AVCC = VCC = 3.5 V to 6.0 V range
5
Operating voltage (V)
Operation assurance range 4
3
2
1
1 Main clock operating frequency
2
3
4
(MHz)
4.0 2.0 Minimum execution time (instruction cycle) Note: The shaded area is assured only for the MB89983.
1.0
(s)
Figure 1
Operating Voltage vs. Main Clock Operating Frequency
Figures 1 indicate the operating frequency of the external oscillator at an instruction cycle of 4/FCH. Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating speed is switched using a gear. Warning: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely reliability and could result in device failure. No warranty is made with respect to uses, operating condition, or combination not represented on the datasheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand.
26
MB89980 Series
2. DC Characteristics
(1) Pin DC characteristics (VCC = +5.0 V) (VSS = 0.0 V, TA = -40C to +85C) Value Unit Remarks Typ. Max. VCC + 0.3 V
Parameter
Symbol
Pin P00 to P07, P10 to P17, P20 to P27 RST, MOD0, MOD1, EC, INT10 to INT13, INT20 to INT27 P00 to P07, P10 to P17, P20 to P27 RST, MOD0, MOD1, EC, INT10 to INT13, INT20 to INT27 P20 to P27 P40 to P47, P60 to P65 P50 to P53 P00 to P07, P10 to P17 P30 P00 to P07, P10 to P17, P30 P20, P22 to P25, P50 to P53, P62 to P65, P70 to P71 P21, P26, P27, P40 to P47, P60, P61 RST
Condition
Min. 0.7 VCC
VIH "H" level input voltage VIHS
0.8 VCC
VCC + 0.3
V
VIL "L" level input voltage VILS
VSS - 0.3 VSS - 0.3
0.3 VCC
V
0.2 VCC
V P20 to P27 , P40 to P47, and P60 to P65 without pullup resistor only
Open-drain output pin application voltage
VD1
VSS - 0.3 VSS - 0.3 IOH = -2.0 mA IOH = -6.0 mA IOL = 1.8 mA 2.4 4.0

VSS + 6.0
V
VD2 "H" level output voltage VOH1 VOH2 VOL1
VCC + 0.3 0.4
V V V V
"L" level output voltage
VOL2
IOL = 4.0 mA
0.4
V
VOL3 VOL4 Input leakage current (Hi-z output leakage ILI current)
IOL = 8.0 mA IOL = 4.0 mA

0.4 0.4 5
V V A Without pull-up resistor
P00 to P07, P10 to P17, 0.45 V < VI < VCC MOD0, MOD1, P30
(Continued)
27
MB89980 Series
(Continued)
(VSS = 0.0 V, TA = -40C to +85C) Value Unit Remarks Typ. Max. -- 5 A Without pull-up resistor Without pull-up resistor
Parameter
Symbol
Pin P20 to P27, P40 to P47, P60 to P65, P70, P71 P50 to P53 P00 to P07, P10 to P17, P20 to P27, P40 to P47, P50 to P53, P60 to P65, RST COM0 to COM3
Condition
Min. --
Open-drain output leakage current
ILO1
0.45 V < VI < 6.0 V
ILO2
0.45 V < VI < VCC
--
--
5
A
Pull-up resistance
RPULL
VI = 0.0 V
25
50
100
k
With pull-up resistor
Common output impedance Segment output impedance LCD divided resistance
RVCOM RVSEG RLCD
-- V1 to V3 = +5.0 V -- Between VCC and V0 300
-- -- 500
2.5 15 750
k k k A pF
SEG0 to SEG13 -- V0 to V3, COM0 to COM3, SEG0 to SEG13 Other than VCC, VSS f = 1 MHz
LCD controller/driver ILCDL leakage current Input capacitance CIN
--
-- --
-- 10
1 --
Note: For pins which serve as the segment (SEG0 to SEG13) and ports (P40 to P47, P50 to P53, and P60 to P65), see the port parameter when these pins are used as ports and the segment parameter when they are used as segments.
28
MB89980 Series
(2) Pin DC Characteristics (VCC = +3.0 V) (VCC = 3.0 V, VSS = 0.0 V, TA = -40C to +85C) Value Unit Remarks Min. Typ. Max. 2.4 2.4 -- -- -- -- V V
Parameter "H" level output voltage
Symbol VOH1 VOH2
Pin P00 to P07, P10 to P17 P30 P00 to P07, P10 to P17, P20 to P27, P30, P50 to P53, P62 to P65, P70 to P71 RST P21, P26, P27 P40 to P47, P60, P61 P00 to P07, P10 to P17, P20 to P27, P40 to P47, P50 to P53, P60 to P65, P70 to P71 RST
Condition IOH = -1.0 mA IOH = -3.0 mA
VOL1 "L" level output voltage VOL2 VOL3
IOL = 1.8 mA
--
--
0.4
V
IOL = 1.8 mA IOL = 3.6 mA
-- --
-- --
0.4 0.4
V V
Pull-up resistance
RPULL
VI = 0.0 V
50
100
150
k
With pull-up resistor
29
MB89980 Series
(3) Power Supply Current Characteristics (MB89983) (VSS = 0.0 V, TA = -40C to +85C) Value Unit Remarks Typ. Max. 5.0 10.0 mA
Parameter
Symbol
Pin
Condition FCH = 4.2 MHz, VCC = 5.0 V tinst*2 = 4/FCH Main clock operation mode FCH = 4.2 MHz, VCC = 3.0 V tinst*2 = 64/FCH Main clock operation mode FCL = 32.768 kHz, VCC = 3.0 V tinst*2 = 2/FCL Subclock operation mode FCH = 4.2 MHz, VCC = 5.0 V tinst*2 = 4/FCH Main clock sleep mode FCH = 4.2 MHz, VCC = 3.0 V tinst*2 = 64/FCH Main clock sleep mode FCL = 32.768 kHz, VCC = 3.0 V tinst*2 = 2/FCL Subclock sleep mode FCL = 32.768 kHz, VCC = 3.0 V Watch mode TA = +25xC, VCC = 5.0 V Stop mode
Min. --
ICC1
ICC2
--
1.5
2.0
mA
ICCL
--
0.05
0.1
mA
ICCS1 Power supply current*1
VCC
--
2.5
5.0
mA
MB89983
ICCS2
--
1.0
1.5
mA
ICCSL ICCT ICCH IA AVCC
-- -- -- --
25 10 0.1 1.0
50 15 1.0 3.0
A A A mA When A/D conversion is activated
FCH = 4.2 MHz, VCC = 5.0 V
*1: The power supply current is measured at the external clock, open output pins, and the external LCD dividing resistor (or external input for the reference voltage). *2: For information on tinst, see "(4) Instruction Cycle" in "4. AC Characteristics."
30
MB89980 Series
4. AC Characteristics
(1) Reset Timing (VCC = +5.0 V 10 %, VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Max. -- 48 tXCYL 24 tXCYL -- -- ns ns
Parameter RST "L" pulse width RST "H" pulse width
Symbol tZLZH tZHZL
tZLZH
tZHZL 0.8 VCC
RST
0.2 VCC 0.2 VCC 0.2 VCC
(2) Power-on Reset (VSS = 0.0 V, TA = -40C to +85C) Parameter Power supply rising time Power supply cut-off time tR tOFF Symbol Condition -- -- Value Min. -- 1 Max. 50 -- Unit ms ms Remarks Power-on reset function only Due to repeated operations
Note: Make sure that power supply rises within the selected oscillation stabilization time. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.
tR 2.0 V
tOFF
VCC
0.2 V
0.2 V
0.2 V
31
MB89980 Series
(3) Clock Timing (VSS = 0.0 V, TA = -40C to +85C) Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rising/falling time Symbol FCH FCL tHCYL tLCYL PWH PWL tCR tCF Pin X0, X1 X0A, X1A X0, X1 X0A, X1A X0 X0 Value Min. 1 -- 238 -- 20 -- Typ. -- 32.768 -- 30.5 -- -- Max. 4.2 -- 1000 -- -- 24 Unit MHz kHz ns s ns External clock ns Remarks Main clock Subclock Main clock Subclock
Main Clock Timing and Conditions
tHCYL 0.8 VCC 0.2 VCC PWH tCF PWL tCR
X0
Main Clock Conditions
When a crystal or ceramic resonator is used X0 X1 FCH FCH C0 C1 C When the CR oscillation option is used
When an external clock is used
X0
X1 Open
X0
X1 FCH R
32
MB89980 Series
Subclock Timing and Conditions
tLCYL
X0A
0.8 VCC
Subclock Conditions
When a crystal or ceramic oscillator is used
When the single-clock option is used
X0A FCL
X1A Rd
X 0A
X 1A
Open
C0
C1
(4) Instruction Cycle (VSS = 0.0 V, TA = -40C to +85C) Parameter Instruction cycle (minimum execution time) Symbol tinst Value (typical) 4/FCH, 8/FCH, 16/FCH, 64/FCH 2/FCL Unit s s Remarks (4/FCH) tinst = 1.0 s at FCH = 4 MHz tinst = 62 s at FCL = 32.768 kHz
33
MB89980 Series
(5) Peripheral Input Timing (VCC = +5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Pin Unit Remarks Min. Max. INT10 to INT13, EC INT20 to INT27 1 tinst* 1 tinst* 2 tinst* 2 tinst* -- -- -- -- s s s s
Parameter Peripheral input "H" pulse width 1 Peripheral input "L" pulse width 1 Peripheral input "H" pulse width 2 Peripheral input "L" pulse width 2
Symbol tILIH1 tIHIL1 tILIH2 tIHIL2
* : For information on tinst, see "(4) Instruction Cycle."
t IHIL1
t ILIH1
INT10 to 13, EC
0.2 VCC
0.8 VCC 0.2 VCC
0.8 VCC
t IHIL2
t ILIH2
INT20 to 27
0.8 VCC 0.2 VCC 0.2 VCC 0.8 VCC
34
MB89980 Series
5. A/D Converter Electrical Characteristics
(3 MHz, AVCC = VCC = +3.5 V to +6.0 V, AVSS = VSS = 0.0 V, TA = -40C to +85C) Parameter Resolution Total error Linearity error Differential linearity error Zero transition voltage Full-scale transition voltage Interchannel disparity A/D mode conversion time Sense mode conversion time Analog port input current IAI Analog input voltage Reference voltage -- -- AVR = 5.0 V, when A/D conversion is activated AVR = 5.0 V, when A/D conversion is stopped -- AN0 to AN3 -- VOT -- VFST AVR - 3.0 LSB AVR - 1.5 LSB -- -- -- -- 0.0 2.0 -- 44 tinst 12 tinst -- -- -- AVR 0.5 -- -- 10 AVR AVCC mV LSB ms ms A V V A AVR = AVCC -- Symbol Pin Condition -- Value Min. -- -- -- -- Typ. -- -- -- -- Max. 8 1.5 1.0 0.9 Unit bit LSB LSB LSB mV Remarks
AVSS - 1.0 LSB AVSS + 0.5 LSB AVSS + 2.0 LSB
IR Reference voltage supply current IRH AVR
--
100
--
--
--
1
A
(1) A/D Glossary * Resolution Analog changes that are identifiable with the A/D converter. When the number of bits is 8, analog voltage can be divided into 28=256. * Linearity error (unit: LSB) The deviation of the straight line connecting the zero transition point ("0000 0000" "0000 0001") with the full-scale transition point ("1111 1111" "1111 1110") from actual conversion characteristics * Differential linearity error (unit: LSB) The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value * Total error (unit: LSB) The difference between theoretical and actual conversion values
35
MB89980 Series
Digital output 1111 1111 . . . . . . . . . . . 0000 0000 0000 1111 1110 Actual conversion value Theoretical conversion value Linearity error = 1 LSB = AVR 256 VNT - (1 LSB x N + VOT) 1 LSB V(N+1)T - VNT 1 LSB -1
(1 LSB x N + VOT)
Defferential linearity error =
Total error = Linearity error 0010 0001 0000
VNT - (1 LSB x N + 1 LSB) 1 LSB
VOT
VNT V(N + 1)T
VFST
Analog input
(2) Precautions * Input impedance of analog input pins The A/D converter contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for eight instruction cycles after activating A/D conversion. For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output impedance of the external circuit low (below 10 k). Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about 0.1 F for the analog input pin.
Analog Input Equivalent Circuit
Sample hold circuit . C = 33 pF .
Analog input pin Comparator If the analog input impedance is higher than 10 k, it is recommended to connect an external capacitor of approx. 0.1 F. . R = 6 k . Close for 8 instruction cycles after activating A/D conversion. Analog channel selector
* Error The smaller the |AVR - AVSS|, the greater the error would become relatively.
36
MB89980 Series
s EXAMPLE CHARACTERISTICS
1. "L" Level Output Voltage
VOL1 vs. IOL
VOL1 (V)
0.6
VCC = 2.5 V VCC = 3.0 V VCC = 2.0 V VCC = 4.0 V
VOL2 vs. IOL
VOL2 (V) VCC = 2.0 V 1.0 TA = +25C 0.9 0.8 0.7 0.6 VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V VCC = 2.5 V VCC = 3.0 V
TA = +25C
0.5 0.4 0.3 0.2 0.1 0
VCC = 5.0 V VCC = 6.0 V
0.5 0.4 0.3 0.2 0.1
0
1
2
3
4
5
6
7
8
9
10 IOL (mA)
0
0
2
4
6
8
10
12 14
16 18
20 IOL (mA)
2. "H" Level Output Voltage
VCC - VOH1 vs. IOH VCC - VOH1 (V) VCC = 2.0 V VCC = 2.5 V VCC = 3.0 V 1.0 TA = +25C 0.9
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 -1 -2 -3 -4 -5 IOH (mA)
VCC - VOH2 vs. IOH VCC - VOH2 (V) VCC = 2.0 V VCC = 2.5 V 1.0 TA = +25C 0.9
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 -1 -2 -3 -4 -5 -6 -7 -8
VCC = 3.0 V
VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V
VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V
-9 -10 IOH (mA)
37
MB89980 Series
3. "H" Level Input Voltage/"L" level Input Voltage
CMOS input
VIN (V) 5.0 TA = +25C 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 1 2 3 4 5 6 7 VCC (V)
CMOS hysteresis input
VIN (V) 5.0 TA = +25C 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 1 2 3 4 5 6 7 VCC (V) VILS VIHS
VIHS: Threshold when input voltage in hysteresis characteristics is set to "H" level VILS: Threshold when input voltage in hysteresis characteristics is set to "L" level
4. Power Supply Current (External Clock)
ICC1 vs VCC (Mask ROM products) ICC1 (mA) 5 TA = +25 C 4
0.8
o
ICC2 vs VCC (Mask ROM products) ICC2 (mA) 1 TA = +25 C
o
FCH = 4.2 MHz 3 FCH = 3 MHz 2
0.4 FCH = 3 MHz 0.6 FCH = 4.2 MHz
1
FCH = 1MHz
0.2
FCH = 1 MHz
0
1
2
3
4
5
6
7 VCC (V)
0
1
2
3
4
5
6
7 VCC (V)
(Continued)
38
MB89980 Series
(Continued)
ICC1S vs VCC (Mask ROM products) ICC1S (mA) 1 TA = +25 C 0.8 FCH = 3 MHz 0.6
0.3 FCH = 3 MHz 0.4 FCH = 4.2 MHz
o
ICC2S vs VCC (Mask ROM products) ICC2S (mA)
FCH = 4.2 MHz
0.5 TA = + 25 C
o
0.4 FCH = 1 MHz 0.2
0.2 FCH = 1 MHz 0.1
0
1
2
3
4
5
6
7 VCC (V)
0
1
2
3
4
5
6
7 VCC (V)
ICCL vs VCC (Mask ROM products) ICCL (mA) 100 TA = + 25 C 80
o
ICCT vs VCC ICCT (mA) 4 3.6 3.2 2.8
o
TA = + 25 C
60 FCL = 32.768 kHz 40
2.4 FCL = 32.768kHz 2 1.6 1.2
20
0.8 0.4
0 1 2 3 4 5 6 7 VCC (V)
0
1
2
3
4
5
6
7 VCC (V)
(Continued)
39
MB89980 Series
(Continued)
ICCSL vs. VCC ICCSL (mA) 200 TA = +25C 180 160 140 120 100 80 60 40 20 0 1 2 3 4 5 6 7 VCC (V)
IR vs. AVR
FCL = 32.768 kHz
IA vs AVCC IA (mA) 4 3.5 3 2.5 2 1.5
40
o
IR (uA) 120
TA = + 25 C FCH = 4 MHz
TA = + 25 C 100
o
80
60
1
20
0.5 0 1.5
0
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5 AVCC(V)
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5 AVR (V)
(Continued)
5. Pull-up Resistance
RPULL vs. VCC
RPULL (k) 1,000 500
100 50 TA = +85C TA = +25C TA = -40C 10 1 2 3 4 5 6 7 VCC (V)
40
MB89980 Series
s INSTRUCTIONS
Execution instructions can be divided into the following four groups: * * * * Transfer Arithmetic operation Branch Others
Table 1 lists symbols used for notation for instructions. Table 1 Symbol dir off ext #vct #d8 #d16 dir: b rel @ A AH AL T TH TL IX Direct address (8 bits) Offset (8 bits) Extended address (16 bits) Vector table number (3 bits) Immediate data (8 bits) Immediate data (16 bits) Bit direct address (8:3 bits) Branch relative address (8 bits) Register indirect (Example: @A, @IX, @EP) Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of accumulator A (8 bits) Lower 8 bits of accumulator A (8 bits) Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of temporary accumulator T (8 bits) Lower 8 bits of temporary accumulator T (8 bits) Index register IX (16 bits) Instruction Symbols Meaning
(Continued)
41
MB89980 Series
(Continued)
Symbol EP PC SP PS dr CCR RP Ri x (x) (( x )) Extra pointer EP (16 bits) Program counter PC (16 bits) Stack pointer SP (16 bits) Program status PS (16 bits) Accumulator A or index register IX (16 bits) Condition code register CCR (8 bits) Register bank pointer RP (5 bits) General-purpose register Ri (8 bits, i = 0 to 7) Indicates that the very x is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Indicates that the contents of x is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) The address indicated by the contents of x is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Meaning
Columns indicate the following: Mnemonic: ~: #: Operation: TL, TH, AH: Assembler notation of an instruction Number of instructions Number of bytes Operation of an instruction A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: * "-" indicates no change. * dH is the 8 upper bits of operation description data. * AL and AH must become the contents of AL and AH immediately before the instruction is executed. * 00 becomes 00. N, Z, V, C: OP code: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F This indicates 48, 49, ... 4F.
42
MB89980 Series
Table 2 Mnemonic MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A MOVW ext,A MOVW @EP,A MOVW EP,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP,#d16 MOVW IX,A MOVW A,IX MOVW SP,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC ~ 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 # 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 Transfer Instructions (48 instructions) Operation (dir) (A) ( (IX) +off ) (A) (ext) (A) ( (EP) ) (A) (Ri) (A) (A) d8 (A) (dir) (A) ( (IX) +off) (A) (ext) (A) ( (A) ) (A) ( (EP) ) (A) (Ri) (dir) d8 ( (IX) +off ) d8 ( (EP) ) d8 (Ri) d8 (dir) (AH),(dir + 1) (AL) ( (IX) +off) (AH), ( (IX) +off + 1) (AL) (ext) (AH), (ext + 1) (AL) ( (EP) ) (AH),( (EP) + 1) (AL) (EP) (A) (A) d16 (AH) (dir), (AL) (dir + 1) (AH) ( (IX) +off), (AL) ( (IX) +off + 1) (AH) (ext), (AL) (ext + 1) (AH) ( (A) ), (AL) ( (A) ) + 1) (AH) ( (EP) ), (AL) ( (EP) + 1) (A) (EP) (EP) d16 (IX) (A) (A) (IX) (SP) (A) (A) (SP) ( (A) ) (T) ( (A) ) (TH),( (A) + 1) (TL) (IX) d16 (A) (PS) (PS) (A) (SP) d16 (AH) (AL) (dir): b 1 (dir): b 0 (AL) (TL) (A) (T) (A) (EP) (A) (IX) (A) (SP) (A) (PC) TL - - - - - AL AL AL AL AL AL AL - - - - - - - - - AL AL AL AL AL AL - - - - - - - - - - - - - - - AL AL - - - - TH - - - - - - - - - - - - - - - - - - - - - AH AH AH AH AH AH - - - - - - - - - - - - - - - - AH - - - - AH - - - - - - - - - - - - - - - - - - - - - dH dH dH dH dH dH dH - - dH - dH - - - dH - - AL - - - dH dH dH dH dH NZVC ---- ---- ---- ---- ---- ++-- ++-- ++-- ++-- ++-- ++-- ++-- ---- ---- ---- ---- ---- ---- ---- ---- ---- ++-- ++-- ++-- ++-- ++-- ++-- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ++++ ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- OP code 45 46 61 47 48 to 4F 04 05 06 60 92 07 08 to 0F 85 86 87 88 to 8F D5 D6 D4 D7 E3 E4 C5 C6 C4 93 C7 F3 E7 E2 F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0
Notes: * During byte transfer to A, T A is restricted to low bytes. * Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F 2MC-8 family)
43
MB89980 Series
Table 3 Mnemonic ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A ROLC A CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir ~ 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 # 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 Arithmetic Operation Instructions (62 instructions) Operation (A) (A) + (Ri) + C (A) (A) + d8 + C (A) (A) + (dir) + C (A) (A) + ( (IX) +off) + C (A) (A) + ( (EP) ) + C (A) (A) + (T) + C (AL) (AL) + (TL) + C (A) (A) - (Ri) - C (A) (A) - d8 - C (A) (A) - (dir) - C (A) (A) - ( (IX) +off) - C (A) (A) - ( (EP) ) - C (A) (T) - (A) - C (AL) (TL) - (AL) - C (Ri) (Ri) + 1 (EP) (EP) + 1 (IX) (IX) + 1 (A) (A) + 1 (Ri) (Ri) - 1 (EP) (EP) - 1 (IX) (IX) - 1 (A) (A) - 1 (A) (AL) x (TL) (A) (T) / (AL),MOD (T) (A) (A) (T) (A) (A) (T) (A) (A) (T) (TL) - (AL) (T) - (A) CA C A (A) - d8 (A) - (dir) (A) - ( (EP) ) (A) - ( (IX) +off) (A) - (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) TL - - - - - - - - - - - - - - - - - - - - - - - dL - - - - - - - - - - - - - - - - - - - - - - - TH - - - - - - - - - - - - - - - - - - - - - - - 00 - - - - - - - - - - - - - - - - - - - - - - - AH - - - - - dH - - - - - - dH - - - - dH - - - dH dH 00 dH dH dH - - - - - - - - - - - - - - - - - - - - NZVC ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++- ---- ---- ++-- +++- ---- ---- ++-- ---- ---- ++R- ++R- ++R- ++++ ++++ ++-+ ++-+ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- OP code 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 to DF D3 D2 D0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65
(Continued)
44
MB89980 Series
(Continued)
Mnemonic AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP ~ 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 # 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 Operation (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (dir) - d8 ( (EP) ) - d8 ( (IX) + off) - d8 (Ri) - d8 (SP) (SP) + 1 (SP) (SP) - 1 Table 4 Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI ~ 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 # 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 TL - - - - - - - - - - - - - - - TH - - - - - - - - - - - - - - - AH - - - - - - - - - - - - - - - NZVC ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++++ ++++ ++++ ++++ ---- ---- OP code 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1
Branch Instructions (17 instructions) Operation TL - - - - - - - - - - - - - - - - - TH - - - - - - - - - - - - - - - - - AH - - - - - - - - - - - - - - dH - - NZVC ---- ---- ---- ---- ---- ---- ---- ---- -+-- -+-- ---- ---- ---- ---- ---- ---- Restore OP code FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30
If Z = 1 then PC PC + rel If Z = 0 then PC PC + rel If C = 1 then PC PC + rel If C = 0 then PC PC + rel If N = 1 then PC PC + rel If N = 0 then PC PC + rel If V N = 1 then PC PC + rel If V N = 0 then PC PC + reI If (dir: b) = 0 then PC PC + rel If (dir: b) = 1 then PC PC + rel (PC) (A) (PC) ext Vector call Subroutine call (PC) (A),(A) (PC) + 1 Return from subrountine Return form interrupt Table 5
Other Instructions (9 instructions) Operation TL - - - - - - - - - TH - - - - - - - - - AH - dH - - - - - - - NZVC ---- ---- ---- ---- ---- ---R ---S ---- ---- OP code 40 50 41 51 00 81 91 80 90
Mnemonic PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI
~ 4 4 4 4 1 1 1 1 1
# 1 1 1 1 1 1 1 1 1
45
46
3 PUSHW POPW MOV MOVW CLRI A A A,ext A,PS SETC SETI CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC 4 5 6 7 8 9 A B C D E F CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP,A A,SP XCH A A, T A A A XOR AND OR MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX
L
H
0
1
2
0
NOP
SWAP
RET
RETI
1
MULU
DIVU
A
A
JMP CALL PUSHW POPW MOV MOVW CLRC addr16 addr16 IX IX ext,A PS,A
2
ROLC
CMP
ADDC
SUBC
A
A
A
s INSTRUCTION MAP
3
RORC
CMPW
A XOR AND OR DAA A,#d8 A,#d8 A,#d8 DAS
A
ADDCW SUBCW XCHW XORW ANDW ORW MOVW MOVW CLRB BBC INCW DECW MOVW MOVW A A A, T A A A @A,T A,@A dir: 3 dir: 3,rel EP EP EP,A A,EP CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC
MB89980 Series
4
MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8
5
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP,#d16 A,SP MOV @IX +d,A CMP @EP,#d 8 AND XOR @A,IX A,@IX +d +d OR A,@IX +d MOVW XCHW MOVW CLRB BBC MOVW CMP MOV IX,#d16 A,IX @IX dir: 6 dir: 6,rel A,@IX @IX @IX +d,A +d +d,#d8 +d,#d8 CLRB BBC MOVW MOVW MOVW XCHW dir: 7 dir: 7,rel A,@EP @EP,A EP,#d16 A,EP
6
MOV A,@IX +d
CMP A,@IX +d
ADDC A,@IX +d
SUBC A,@IX +d
7
MOV CMP ADDC SUBC MOV XOR AND OR MOV A,@EP A,@EP A,@EP A,@EP @EP,A A,@EP A,@EP A,@EP @EP,#d 8
8
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R0 A,R0 A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel
DEC R0 DEC R1 DEC R2 DEC R3 DEC R4 DEC R5 DEC R6 DEC R7 R7 R6 R5 R4 R3 R2 R1 R0
CALLV BNC #0 rel CALLV BC #1 CALLV BP #2 CALLV BN #3 CALLV BNZ #4 CALLV BZ #5
9
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R1 A,R1 A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel
rel
A
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R2 A,R2 A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel
rel
B
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R3 A,R3 A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel
rel
C
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R4 A,R4 A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel
rel
D
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R5 A,R5 A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel
rel CALLV BGE #6 rel CALLV BLT #7
E
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R6 A,R6 A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel
F
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R7 A,R7 A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel
rel
MB89980 Series
s MASK OPTIONS
Part number No. 1 Specifying procedure Pull-up resistors (SEG) P00 to P07, P10 to P17, P20 to P27, P40 to P47, P50 to P53, P60 to P65 MB89983 Specify when ordering masking Slectable per pin (The pull-up resistors for P40 to P47 and P60 to P65 are only selectable when these pins are not set as segment/ common outputs. When the A/D is used, P50 to P53 are must not selected.) Selectable MB89P985 Setting with software Selectable per pin by pull-up control registers. (Pull-up resistors are not available for P20 to P27, P40 to P47 and P60 to P65. Furthermore, P50 to P53 must be set to without a pull-up resistor when an A/D converter is used.) Fixed with power-on reset MB89PV980 Setting with software Selectable per pin by pull-up control registers. (Pull-up resistors are not available for P20 to P27, P40 to P47 and P60 to P65. Furthermore, P50 to P53 must be set to without a pull-up resistor when an A/D converter is used.) Fixed with power-on reset
2
Power-on reset (POR) With power-on reset Without power-on reset Selection of oscillation stabilization time (OSC) * The initial value of the oscillation stabilization time for the main clock can be set by selecting the values of the WT1 and WT0 bits on the right. Main clock oscillation type (XSL) Crystal or ceramic resonator CR Reset pin output (RST) With reset output Without reset output Clock mode selection (CLK) Dual-clock mode Single-clock mode
3
Selectable OSC 0 : 22/FCH 1 : 212/FCH 2 : 216/FCH 3 : 218/FCH
Fixed to oscillation stabilization time of 218/FCH (Approx. 62.4 ms).
Fixed to oscillation stabilization time of 218/FCH (Approx. 62.4 ms).
4
Selectable
Crystal or ceramic resonator only Fixed with reset output Selection by version number 101 : Single clock 201 : Dual clock
Crystal or ceramic resonator only Fixed with reset output Selection by version number 101 : Single clock 201 : Dual clock
5
Selectable
6
Selectable
47
MB89980 Series
* Segment Options Part number No. 7 Specifying procedure LCD output pin configuration choices SEG = 3: P40 to P47 segment output P60 to P65 segment output P70, P71 common output SEG = 2: P40 to P43 port output P44 to P47 segment output P60 to P65 segment output P70, P71 common output SEG = 1: P40 to P47 port output P60 to P65 segment output P70, P71 common output SEG = 0: P40 to P47 port output P60 to P65 port output P70, P71 port output MB89983 Specify when ordering masking Specify by the option combinations listed below Specify as SEG = 3
Specify as SEG = 2
Specify as SEG = 1
Specify as SEG = 0
s VERSIONS
Version Mass production product MB89983 MB89983 One-time PROM product MB89P985-101 MB89P985-201 Piggyback product MB89PV980-101 MB89PV980-201 Features Clock mode Single clock Dual clock
48
MB89980 Series
s ORDERING INFORMATION
Part Number MB89983-xxx-PFV MB89983-xxx-PFM MB89P985PFV-101 MB89P985-PFM-101 MB89P985PFV-201 MB89P985-PFM-201 MB89PV980-101 MB89PV980-201
Package 64-pin Plastic LQFP (FPT-64P-M03) 64-pin Plastic QFP (FPT-64P-M09) 64-pin Plastic LQFP (FPT-64P-M03) 64-pin Plastic QFP (FPT-64P-M09) 64-pin Plastic LQFP (FPT-64P-M03) 64-pin Plastic QFP (FPT-64P-M09) 64-pin Ceramic MQFP (MQP-64C-P01) 64-pin Ceramic MQFP (MQP-64C-P01)
Remarks
Single Clock
Dual Clock
Single Clock Dual Clock
49
MB89980 Series
s PACKAGE DIMENSIONS
64-pin Plastic LQFP (FPT-64P-M03)
12.000.20(.472.008)SQ
48
1.50 -0.10 .059 -.004
33
+0.20 +.008
(Mounting height)
10.000.10(.394.004)SQ
49
32
7.50 (.295) REF INDEX
11.00 (.433) NOM
64
17 1 16
+0.08 +.003
Details of "A" part "A" 0.127 -0.02 .005
+0.05 +.002 -.001
LEAD No.
0.500.08 (.0197.0031)
0.18 -0.03 .007 -.001
0.100.10 (STAND OFF) (.004.004)
0.500.20 (.020.008) 0.10(.004) 0 10
C
1995 FUJITSU LIMITED F64009S-2C-5
Dimension in mm (inches)
64-pin Plastic QFP (FPT-64P-M09)
14.000.20(.551.008)SQ
48
12.000.10(.472.004)SQ
33
1.50 -0.10 +.008 .059 -.004
+0.20
(Mounting height)
49
32
9.75 (.384) REF 1 PIN INDEX
13.00 (.512) NOM
64
17
LEAD No.
1
16
Details of "A" part "A"
M
0.65(.0256)TYP
0.300.10 (.012.004)
0.13(.005)
0.127 -0.02 +.002 .005 -.001
+0.05
0.100.10 (STAND OFF) (.004.004)
0.10(.004) 0 10
0.500.20 (.020.008)
C
1994 FUJITSU LIMITED F64018S-1C-2
Dimension in mm (inches)
50
MB89980 Series
64-pin Ceramic MQFP (MQP-64C-P01)
18.70(.736)TYP 16.300.33 (.642.013) 15.580.20 (.613.008) 12.00(.472)TYP 1.20 -0.20 +.016 .047 -.008
+0.40
INDEX AREA
1.000.25 (.039.010)
1.000.25 (.039.010)
1.270.13 (.050.005) 22.300.33 (.878.013) 24.70(.972) TYP 0.30(.012) TYP 18.120.20 12.02(.473) (.713.008) TYP 10.16(.400) 14.22(.560) TYP TYP
18.00(.709) TYP
1.270.13 (.050.005)
0.30(.012)TYP 7.62(.300)TYP 9.48(.373)TYP 11.68(.460)TYP
0.400.10 (.016.004)
0.400.10 (.016.004)
1.20 -0.20 +.016 .047 -.008
+0.40
0.50(.020)TYP
10.82(.426) 0.150.05 MAX (.006.002)
C
1994 FUJITSU LIMITED M64004SC-1-3
Dimension in mm (inches)
51
MB89980 Series
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: (044) 754-3763 Fax: (044) 754-3329
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete information sufficient for construction purposes is not necessarily given. The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies. The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu. Fujitsu reserves the right to change products or specifications without notice. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu. The information contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equipments, undersea repeaters, nuclear control systems or medical equipments for life support.
http://www.fujitsumicro.com/
Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F9902 (c) FUJITSU LIMITED Printed in Japan
52

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